BC Series BIOS POST Codes

Code	LED Display	Description
00h		The system configuration has been displayed. Passing control to INT 19h Bootstrap Loader next.
01h		Processor register test about to start. NMIs are disabled next.
02h		NMIs are disabled. The Opower onO delay is starting.
03h		Power on delay has been completed. Intializations required before the keyboard BAT is done are now in progress.
04h		The initializations required before the keyboard BAT are completed. Reading the keyboard SYS bit to check for soft reset or power-on next.
05h		The soft reset or power-on setting has been determined. Next, enabling the ROM and disabling shadow RAM and Cache Memory, if any.
06h		ROM is enabled. Calculating the ROM BIOS checksum and waiting for the keyboard controller input buffer to be free.
07h		The ROM BIOS checksum test passed and the keyboard controller input buffer is free. Issuing a BAT command to the keyboard controller next.
08h		A BAT command has been issued to the keyboard controller. Verifying the BAT command next.
09h		The keyboard controller BAT result was verified. A keyboard controller command byte is to be written next.
0Ah		A keyboard controller command byte code has been issued. Writing the command byte data next.
0Bh		The keyboard controller command byte has been written. Issuing the Pin 23, 24 blocking and unblocking command next.
0Ch		Pin 23,24 of the keyboard controller has been blocked and unblocked. The keyboard controller NOP command is issued next.
0Dh		The keyboard controller NOP command processing is done. The CMOS RAM shutdown register test is performed next.
0Eh		The CMOS RAM shutdown register Read/Write test passed. Calculating the CMOS RAM checksum and updating the DIAG byte next.
0Fh		The CMOS RAM checksum calculation is done and the DIAG byte is written. CMOS RAM initialization begins next if CMOS RAM is to be initialized during every boot.
10h		CMOS RAM initialization (if any) is done. Next, the CMOS RAM status register is initialized for Date and Time.
11h		The CMOS RAM status register has been initialized. Disabling the DMA and interrupt controllers next.
12h		DMA controllers 1 and 2 and interrupt controllers 1 and 2 are disabled. Disabling the video display and initializing port B next.
13h		The video display is disabled and port B is initialized. Chipset initialization and auto memory detection are about to begin.
14h		Chipset initialization and auto memory detection are done. The 8254 Channel 2 timer test is about to start.
15h		The 8254 Channel 2 timer test is half-completed. The entire 8254 Channel 2 timer test is completed next.
16h		The entire 8254 Channel 2 timer test is done. The 8254 Channel timer test is done next.
17h		The 8254 Channel 1 timer test is done. The 8254 Channel 0 timer test is completed next.
18h		The 8254 Channel 0 timer test is done. About to start memory refresh.
19h		Memory refresh has been started. The memory refresh test is performed next.
1Ah		The memory refresh line is toggling. Checking the 15 second ON/OFF time next.
1Bh		The memory refresh test has been completed. The base 64 KB memory test is about to start.